The present invention relates to a storage device controller, and a method of controlling the storage device controller.
The amount of data to be handled in a computer system has recently increased. In connection with this increase in the data amount, a large-scale storage system equipped with a storage volume which is managed by a RAID (Redundant Arrays of Inexpensive Disks) system for supplying enormous storage resources, referred to as a mid-range class or enterprise class, has recently received widespread attention as a storage system for managing large amounts of data. Furthermore, a technique in which information processing devices are connected to a storage system through a dedicated network (Storage Area Network, hereinafter referred to as a “SAN”) to enable a large amount of access to the storage system at high speed has been developed to efficiently use and manage vast amounts of data.
Furthermore, a storage system called a NAS (Network Attached Storage) has been developed for mutually connecting a storage system and an information processing device through a network using the TCP/IP (Transmission Control Protocol/Internet Protocol) protocol or the like and for implementing access to data based on a file-name indication from the information processing device.
Such a storage system as described above uses a DMA (Direct Memory Access) transfer technique for eliminating transferring of data through the CPU (Central Processing Unit) in order to increase the data access speed. In order to carry out DMA transfer, the CPU writes into a register equipped to a DMA controller, data transfer information needed for data transfer, such as a transfer source storage address, a transfer destination storage address, etc. for data to be transferred, and instructs the DMA controller to start the data transfer. Accordingly, the data transfer is carried out by the DMA controller without involving the CPU in the data transfer (see JP-A-2003-22246).
However, it takes more time to carry out data writing from the CPU into the register of the DMA controller in the data transfer circuit containing the DMA controller as compared with data writing from the CPU into a memory element. Therefore, in a situation in which data transfer occurs frequently, the time needed for the DMA starting processing involving the data writing from the CPU into the register of the DMA controller inhibits an increase in the data access speed.
Furthermore, in a situation in which data input/output control is carried out by using plural CPUs, when data transfer is carried out between memories, each of which is controlled by a respective CPU, the CPU for controlling the DMA controller is required to obtain information on storage addresses, etc. of data in the memories controlled by the other CPUs. Moreover, in a situation in which the data transfer size is different for each memory, the CPU for controlling the DMA controller is required to provide control for adjusting the data transfer size. An increase in the processing load imposed on the CPU for controlling the DMA controller inhibits an increase of the data access speed. Therefore, it has been required to reduce the processing load imposed on the CPU for controlling the DMA controller.